Electrical and Computer Engineering

Trusted 3rd-party module acquisition through proof-carrying hardware intellectual property (PCHIP)

September 27, 2018

4:00 p.m. - 5:30 p.m. ET

Scaife Hall, Room 125

Yiorgos Makris, Ph.D.
Professor
Department of Electrical and Computer Engineering
University of Texas - Dallas

Abstract

The use of 3rd-party hardware intellectual property (IP), acquired in the form of code in a hardware description language (HDL), enables fast development of new electronic systems and is prevalent in both commercial and defense applications. To alleviate the security and trustworthiness concerns arising from 3rd-party hardware IP in a globalized semiconductor industry, we adapted the well-known proof carrying code (PCC) paradigm from the software community to enable formal yet computationally straightforward validation of security-related properties in hardware systems. These properties, agreed upon a priori by the IP vendor and consumer and codified in a temporal logic, outline the boundaries of trusted operation, without necessarily specifying the exact IP functionality. A formal proof is then crafted by the vendor and presented to the consumer, who can automatically validate compliance of the hardware IP to the agreed-upon security properties. In this presentation, I will first review our initial proof-of-concept framework for developing provably trustworthy hardware IP, along with its suitability for supporting information flow tracking (IFT). I will then describe how this framework gradually turned into an ecosystem comprising foundations, libraries, automation, and examples on digital cryptographic circuits. Extensions enabling similar capabilities in the analog and mixed-signal domain will also be briefly discussed. I will conclude by emphasizing the need and pointing out the challenges involved in developing formal solutions in hardware security.

Bio

Yiorgos Makris is a professor of electrical and computer engineering at The University of Texas at Dallas, where he leads the Trusted and RELiable Architectures (TRELA) Research Laboratory. Prior to joining UT Dallas in 2011, he spent 10.5 years as a faculty member in electrical engineering and in computer science at Yale University. He holds a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from the University of California, San Diego, and a Diploma of Computer Engineering and Informatics (1995) from the University of Patras, Greece. His main research interests are in the application of machine learning and statistical analysis in the design of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He is also investigating hardware-based malware detection, forensics and reliability methods in modern microprocessors, as well as on-die learning and novel computational modalities using emerging technologies. His research activities have been supported by NSF, ARO, AFRL, SRC, DARPA, Boeing, IBM, LSI, Intel, Advantest, AMS, and TI. Yiorgos served as the 2016-2017 general chair and the 2013-2014 program chair of the IEEE VLSI Test Symposium, as well as the 2010-2012 program chair of the Test Technology Educational Program (TTEP). He is as an associate editor of IEEE Transactions on Information Forensics and Security, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Design & Test periodical, and the Springer Journal of Electronic Testing: Theory and Applications. He has also served as a guest editor for IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and as a topic coordinator and/or program committee member for several IEEE and ACM conferences. He is a Senior Member of the IEEE, a recipient of the 2006 Sheffield Distinguished Teaching Award, and a recipient of Best Paper Awards from the 2013 Design Automation and Test in Europe (DATE'13) conference and the 2015 VLSI Test Symposium (VTS'15).

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